Schemes for Built-In Self-Test (BIST) of semiconductor devices having digital circuitry may be based on, inside the semiconductor device itself, generating a test stimulus, letting functional circuits of the semiconductor device operate on the test stimulus to obtain responses, collecting the responses and analysing the responses. The test stimulus may be generated by a pseudo-random pattern generator (PRPG). The responses may be collected in a Multi-Input Signature Register (MISR) where a so-called signature is calculated from the responses. Hereto, multiple scan chains may be connected between the pseudo-random pattern generator (PRPG) and the Multi-Input Signature Register (MISR) for shifting test data of the test stimulus into the circuitry under test in a so-called scan phase, to hereby load the multiple scan chains with the test data. Each scan chain is associated with one of multiple functional partitions of the semiconductor devices. After the loading is completed, the partitions operate in their functional context based on the loaded test data in a so-called capture phase. The response of the partitions to the loaded test data is captured in the associated scan chains. Subsequently, all responses are shifted out of the scan chain into a compacting logic, typically by using an exclusive-OR over several responses, and the signature is calculated using a Multi-Input Signature Register (MISR). The signature may then be made available for further analysis, such as comparison with a reference signature associated with expected responses to determine whether the digital circuitry behaved fault-free. The shifting of test data into the circuitry and the shifting of responses out of the scan chain may be done simultaneously. A Built-In Self-Test (BIST) of a digital circuitry may also be referred to as Logic Built-In Self-Test (LBIST). The scan phase may also be referred to as shift phase.
The functional partitions may be configured to operate at different operation frequencies during normal operation of the semiconductor device. These different operation frequencies may further be referred to as functional frequencies. In the capture phase, all functional partitions may operate at their associated operation frequencies, allowing at-speed testing of the functional partitions. An example of a BIST scheme is given in, e.g., U.S. Pat. No. 6,966,021 B2.
The scan phase may use a common shift frequency for all scan chains. The scan phase may use a shift frequency that is different from the functional clock frequencies. The scan phase may in particular use a shift frequency that is lower than the fastest functional clock, for example to reduce the power consumption of the scan phase.
The scan phase may in particular use a shift clock that is established as a divided down version of the fastest functional clock by periodically suppressing one or more successive clock pulses of the fastest functional clock to obtain a so-called punched-out clock. Hereby, a shift clock is obtained with a pulse duration equal to the pulse duration of the fastest functional clock and a cycle time corresponding to a plurality of cycle times of the fastest functional clock. For example, every second, third and fourth clock pulse of four successive clock pulses of the fastest functional clock may be periodically suppressed to obtain a punched-out clock having the same pulse duration as the fastest functional clock but a four times longer cycle time, i.e., a four times lower frequency. The fastest functional clock may, e.g., have a 200 MHz frequency, corresponding to a 2.5 ns clock pulse and a 5.0 ns clock cycle time, and an associated 50 MHz punched-out clock may have the same 2.5 ns clock pulse at a 20.0 ns clock cycle time.
Scan chains associated with functional partitions of different clock domains may be driven with the same punched-out clock, with at least the last flip-flop of each of the scan chains being reactive on the positive edge of the punched-out clock. Physical effects may however result in some non-zero clock skew between the different scan chains, for example resulting from different insertion delays due to synthesizing the scan chains in clock domains of different speed. Hereto, a retiming element, such as a negative-edge triggered flip-flop, may be provided between the scan chains and the MISR to provide a stable data stream, which may be passed on further to a positive-edge triggered flip-flop at the input of the Multi-Input Signature Register (MISR).
Punched-out clocks may also be used in different applications with multiple clock domains, especially where a low-speed clock domain has a clock cycle time that is a multiple of the clock cycle time of a high-speed clock domain.